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(R)
L4973V3.3 - L4973V5.1 L4973D3.3 - L4973D5.1
3.5A STEP DOWN SWITCHING REGULATOR
UPTO 3.5ASTEP DOWNCONVERTER OPERATING INPUT VOLTAGE FROM 8V TO 55V 3.3V AND 5.1V (1%) FIXED OUTPUT, AND ADJUSTABLE OUTPUTS FROM: 0V TO 50V (3.3V type) 5.1V TO 50V (5.1 type) FREQUENCY ADJUSTABLE UP TO 300KHz VOLTAGE FEED FORWARD ZERO LOAD CURRENT OPERATION (min 1mA) INTERNAL CURRENT LIMITING (PULSE BY PULSE AND HICCUP MODE) PRECISE 5.1V (1.5%) REFERENCE VOLTAGE EXTERNALLY AVAILABLE INPUT/OUTPUT SYNCHRONIZATION FUNCTION INHIBIT FOR ZERO CURRENT CONSUMPTION (100A Typ. at VCC = 24V) PROTECTION AGAINST FEEDBACK DISCONNECTION THERMAL SHUTDOWN OUTPUT OVERVOLTAGE PROTECTION SOFT START FUNCTION TYPICAL APPLICATION CIRCUIT (POWERDIP)
MULTIPOWER BCD TECHNOLOGY
POWERDIP (12+3+3)
SO20(12+4+4)
ORDERING NUMBERS: L4973V3.3 (Powerdip) L4973D3.3 (SO20) L4973V5.1 (Powerdip) L4973D5.1 (SO20)
DESCRIPTION The L4973 is a step down monolithic power switching regulator delivering 3.5A at fixed voltages of 3.3V or 5.1V and using a simple external divider output adjustable voltage up to 50V. Realized in BCD mixed technology, the device
VCC (8V to 55V) ROSC CIN C2
7
8
10 12
CBOOT VO(3.3V or 5.1V) L1
1 4,5,6, 13,14,15 16
L4973
17
9 3 11 2 RCOMP
COSC
CSS CCOMP
D1
COUT
D97IN554A
April 2000
1/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
uses an internal power D-MOS transistor (with a typical Rdson of 0.15ohm) to obtain very high efficiency and very fast switching times. Switching frequency up to 300KHz are achievable (the maximum power dissipation of the packages must be observed). A wide input voltage range between 8V to 55V and output voltages regulated from 3.3V to 40V cover the majority of the today applications. Features of this new generation of DC-DC conPIN CONNECTIONS (Top view) verter includes pulse by pulse current limit, hiccup mode for output short circuit protection, voltage feed forward regulation, soft start, input/output synchronization, protection against feedback loop disconnection, inhibit for zero current consumption and thermal shutdown. Packages available are in plastic dual in line, DIP18 (12+3+3) for standard assembly, and SO20 (12+4+4) for SMD assembly.
OSC OUT OUT GND GND GND VCC VCC BOOT
1 2 3 4 5 6 7 8 9
D94IN162A
18 17 16 15 14 13 12 11 10
SYNC SS V5.1 GND GND GND VFB COMP INH
OSC OUT OUT GND GND GND GND VCC VCC BOOT
1 2 3 4 5 6 7 8 9 10
D94IN163A
20 19 18 17 16 15 14 13 12 11
SYNC SS V5.1 GND GND GND GND VFB COMP INH
POWERDIP (12+3+3)
SO20 (12+4+4)
BLOCK DIAGRAM
INH 10(11) V5.1 16(18) VCC 7(8) 8(9) CBOOT CHARGE ZERO CURRENT INHIBIT VREF GOOD INTERNAL REFERENCE INTERNAL SUPPLY 5.1V VCC
5.1V 3.3V
SS
17(19)
SOFT START
HICCUP CURRENT LIMITING
COMP
11(12) THERMAL SHUTDOWN 5.1V 3.3V + E/A CURRENT LIMITING R S Q Q 9(10) BOOT
VFB
PWM
12(13)
+
SYNC
18(20)
OSCILLATOR DRIVER 1(1) OSC 4,5,6,13,14,15 (4,5,6,7,14,15,16,17) GND 2(2) OUT 3(3) OUT
D94IN161B
Pin x = Powerdip Pin (x) = S020
2/16
L4973V3 - L4973V5 - L4973D3 - L4973D5
THERMAL DATA
Symbol Rth(j-pin) Rth(j-amb) Parameter Thermal Resistance Junction to pin Thermal Resistance to Ambient Max. Max. Powerdip 12 60 (*) SO20 15 80 (*) Unit C/W C/W
(*) Package mounted on board.
ABSOLUTE MAXIMUM RATINGS
Symbol DIP-18 V7,V8 V2,V3 I2,I 3 V9-V8 V9 V11 V17 V12 V18 V10 Ptot S0-20 V9,V8 V2,V3 I2,I3 V10-V8 V10 V12 V19 V13 V20 V11 Bootstrap voltage Analogs input voltage (VCC = 24V) Analogs input voltage (VCC = 24V) (VCC = 20V) (VCC = 20V) Inhibit Power dissipation a Tpins 90C (Tamb = 70C no copper area) (Tamb = 70C 4cm copper area on PCB) Power dissipation a Tpins = 90C TJ,TSTG Junction and storage temperature DIP 12+3+3 SO20 Input voltage Output DC voltage Output peak voltage at t = 0.1s f=200KHz Maximum output current Parameter Value 58 -1 -5 int. limit. 14 70 12 13 6 -0.3 5.5 -0.3 Vcc -0.3 5 1.3 2 4 -40 to 150 V V V V V V V V V V W W W W C Unit V V V
PIN FUNCTIONS
Powerdip 11 10 9 18 7,8 2,3 12 SO20 12 11 10 20 8,9 2,3 13 NAME COMP INH BOOT SYNC Vcc OUT VFB DESCRIPTION E/A output to be used for frequency compensation A logic signal (active high) disables the device (sleep mode operation). If not used it must be connected to GND; if floating the device is disabled. A capacitor connected between this pin and the output allows to drive the internal D-MOS. Input/Output synchronization. Unregulated DC input voltage Stepdown regulator output. Stepdown feedback input. Connecting the output directly to this pin results in an output voltage of 3.3V for the L4973V3.3 and 5.1V. An external resistive divider is required for higher output voltages. For output voltage less than 3.3V, see note ** and Figure 32. Reference voltage externally available. Signal ground An external resistor connected between the unregulated input voltage and Pin 1 and a capacitor connected from Pin 1 to ground fixes the switching frequency. (Line feed forward is automatically obtained)
16 4,5,6 13,14,15 1
18 4,5,6,7 14,15,16,17 1
V5.1 GND OSC
3/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
ELECTRICAL CHARACTERISTICS ( Refer to the test circuit,VCC = 24V; Tj = 25C, COSC = 2.7nF; ROSC = 20K; unless otherwise specified) * = specifications referred to TJ from 0 to 125C.
Symbol Parameter Test Conditions VO = VREF to 40V; IO = 3.5A IO = 1A IO = 0.5A to 3.5A VCC = 8V to 55V IO = 1A IO = 0.5A to 3.5A VCC = 8V to 40V VCC = 10.5V IO = 3.5A VCC = 8V to 55V VO = 5.1V; IO = 3.5A VO = 3.3V; IO = 3.5A Vi = VCC +2VRMS VO = Vref; IO = 1A; fripple = 100Hz VCC = 8V to 55V Min. Typ. Max. 55 5.1 5.1 5.1 3.36 3.36 3.36 0.15 4.5 90 85 100 5.15 5.20 5.25 3.393 3.427 3.46 0.22 0.35 5.5 Unit V V V V V V V A % % KHz dB %
DYNAMIC CHARACTERISTICS Input Voltage Range (*)
Output Voltage L4973V5.1 Output Voltage L4973V3.3 RDSON Maximum Limiting Current Efficiency Switching Frequency Supply Voltage Ripple Rejection Switching Frequency Stability vs, Supply Voltage Reference Voltage Iref = 0 to 20mA; VCC = 8 to 55V Iref = 0mA; VCC = 8 to 55V Vref = 0 to 5mA; VCC = 0 to 20mA
* * * * * *
8 5.05 5.00 4.95 3.326 3.292 3.26
4
90 60
110
fsw
2
5
REFERENCE SECTION
*
5.025 4.950
5.1 5.1 5 2 6 65 45 22
5.175 5.250 10 10 25 100 60 30
V V mV mV mV mA A A
Line Regulation Load Regulation Short Circuit Current
30 30 15
SOFT START
Soft Start Charge Current Soft Start Discharge Current
INHIBIT
High Level Voltage Low Level Voltage Isource High Level Isource Low Level
VINH = 3V VINH = 0.8V Duty Cycle = 50% Duty Cycle = 0 VCC = 24V; VINH = 5V VCC = 55V; VINH = 5V
* * * *
3.0 10 10 16 15 4 2.7 100 150 0.8 50 50 6 4 200 300
V V A A mA mA A A V V A A
DC CHARACTERISTICS
Total Operating Quiescent Current Quiescent Current Total stand-by quiescent current
ERROR AMPLIFIER
High Level Output Voltage Low Level Output Voltage Source Bias Current Source Output Current 4/16 11.0 1 200 2 300 0.65 3 600
L4973V3 - L4973V5 - L4973D3 - L4973D5
ELECTRICAL CHARACTERISTICS (continued)
Sink Output Current Supply Voltage Ripple Rejection DC Open Loop Gain Transconductance VCOMP = VFB CREF =4.7F 1-5mA load current RL = Icomp = -0.1 to 0.1mA; Vcomp = 6V 200 60 300 80 A dB
50
60 2.5
dB mS
OSCILLATOR SECTION
Ramp valley Ramp peak Maximum Duty Cycle Maximum Frequency VCC = 8V VCC = 55V Duty Cycle = 0%; R OSC = 13K; COSC = 820pF; VCC = 8V to 55V VCC = 8V to 55V Isource = 3mA no load, Vsync = 4.5V 3.5 0.15 4 0.20 0.25 4.5 0.35 0.9 0.45 0.78 1.9 9 95 0.85 2.1 9.6 97 0.92 2.3 10.2 500 V V V % KHz
SYNC FUNCTION
High Input Voltage Low Input Voltage Slave Sink Current Master Output Amplitude Output Pulse Width
(*) Pulse testing with a low duty cycle. (**) The maximum power dissipation of the package must be observed.
V V mA V s
Figure 1. Evaluation Board Circuit
VCC
(DIP18)
R2
7,8 1 17
12
L4973
11 10
9 C8 L1 VO R3
C1
C2
C7
16
4,5,6 2,3 13,14,15
C3
C4
C5
R1 C6
D1
3x C0
C12 R4
D97IN515B
C1=1000F/63V C2=220nF/63V C3=470nF C4=1F/50V C5=220pF C6=22nF C7=2.7nF C8=220nF/63V C0=100F/40V(C9,C10,C11) C12=Optional (220nF) L1=150H KOOL 77310 - 40 Turns - 0.9mm R1=9.1K R2=20K D1=GI SB560
L4973 V3.3
VO(V) 3.3 5.1 12 15 18 24 R3(K) 0 2.7 12 16 20 30 4.7 4.7 4.7 4.7 4.7 R4(K) VO(V) 5.1 12 15 18 24
L4973 V5.1
R3(K) 0 6.2 9.1 12 18 4.7 4.7 4.7 4.7 R4(K)
5/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
Typical Performance (Using Evaluation Board) fsw = 100kHz
Output Voltage 3.3V 5.1V 12V Output Ripple 20mV 20mV 30mV Efficiency 81.5 (%) 86.7 (%) 93.5 (%) Line Regulator Io = 3.5A VCC = 8 to 50V 3mV 3mV 3mV (VCC =15 to 50V) Load Regulator VCC =35V IO = 1 to 3.5A 6mV 6mV 4mV
Figure 1a: Evaluation Board (Components Side)
Figure 1b: Evaluation Board (Solder Side)
6/16
L4973V3 - L4973V5 - L4973D3 - L4973D5
Figure 1c: Application Circuit (see fig. 1 part list)
VCC R2 INH SYNC
7,8 1 17
10
18
9
C8
L4973V5.1
11 4,5,6 13,14,15 12 L1 2,3 Vo
C1
C2
C7
16
C3
C4
C5
R1 C6
D1
3x C0
C12
D97IN665A
Figure 1d: Application Circuit (see fig. 1 part list)
VCC R2 INH SYNC
7,8 1 17
10
18
9
C8
L4973V3.3
11 4,5,6 13,14,15 L1 12 2,3 Vo
C1
C2
C7
16
C3
C4
C5
R1 C6
D1
3x C0
C12
D97IN664A
Figure 2: Quiescent Drain Current vs. Input Voltage (0% Duty Cycle)
Ibias (mA) 5.0 4.5 4.0
100KHz-R2=20K C7=2.7nF Tamb=25C 0% DC
Figure 3: Quiescent Drain Current vs. Junction Temperature
Ibias (mA)
D97IN634
200KHz-R2=22K C7=1.2nF
D97IN633A
200KHz-R2=22K C7=1.2nF
4.0
100KHz-R2=20K C7=2.7nF
3.5
3.5
0Hz
0% DC VCC = 35V
3.0 2.5 2.0 0 10 20 30 40 50 VCC(V)
3.0
0Hz
2.5 -50
0
50
100
Tj(C)
7/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
Figure 4: Stand by Drain Current vs. input Voltage
Ibias (A)
Vinh = 5V
Figure 5: Reference Voltage vs. Junction Temperature (Pin 16)
VREF (V)
Pin 16
D97IN635A
D97IN637
150
25C
5.15
Vcc=35V
5.1
100
125C
5.05
50 0 10 20 30 40 50 VCC(V)
5.0 -40 -20
0
20
40
60
80 100 Tj(C)
Figure 6: Reference Voltage vs. Input Voltage (Pin 16)
VREF (V)
Tj=25C Pin 16
Figure 7: Reference Voltage vs. Reference Input Current
VREF (V)
D97IN638
D97IN636A
5.15
5.2
Vcc=40V
5.1
5.1
Vcc=10V
5.05
5.0
Tj=25C
5.0
0
10
20
30
40
50 VCC(V)
4.9 0 10 20 30 40 50 IREF(mA)
Figure 8: Inhibit Current vs. Inhibit Voltage (Pin 10)
Iinh (A)
Vcc=35V Pin 10 Tj=0C
Figure 9: Line Regulation (see fig. 1)
VO (V)
D97IN639A
D97IN651
100
5.12
Tj C 5 =2
Tj=125C
50
Tj=125C
5.1
Tj=25C
0
5.08
IO = 1A
-50 8/16
5.06
0 5 10 15 Vinh(V)
0
10
20
30
40
50
VCC(V)
L4973V3 - L4973V5 - L4973D3 - L4973D5
Figure 10: Load Regulation (see fig. 1c)
VO (V)
VCC = 35V
Figure 11: Line Regulation (see fig. 1d)
VO (V) 3.35 3.34
Tj=125C
D97IN640
D97IN660A
5.15
Tj=125C
5.1
Tj=25C
Tj=25C
3.33 3.32
5.05
3.31
IO = 1A
5.0
0
1
2
3
IO(A)
3.3
0
10
20
30
40
50
VCC(V)
Figure 12: Load Regulation (see fig. 1d)
VO (V) 3.35 3.34
Tj=125C VCC = 35V
Figure 13: Switching Frequency vs.R2 and C7 (fig. 1)
fsw (KHz) 500 200 100 50
0.8 2nF 1.2 nF
2.2n F
D97IN661
D97IN630
Tamb=25C
3.33 3.32 3.31 3.3
Tj=25C
3.3n
F 4.7n F
20 10 5 0 20 40
5.6n
F
0
1
2
3
IO(A)
60
80
R2(K)
Figure 14: Switching Frequency vs. Input Voltage
fsw (KHz)
Tamb=25C
Figure 15: Switching Frequency vs. Junction temperature (see fig. 1)
fsw (KHz)
D97IN632
D97IN631
105
105
100
100
95
95
90
0
10
20
30
40
50 VCC(V)
90 -50 0 50 100 Tj(C)
9/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
Figure 16: Dropout Voltage Between pin 7,8 and 2,3
V (V)
Tj=125C
Figure 17: Efficiency vs. Output Voltage (see fig.1)
(%) 98
100KHz
D97IN643
D97IN641
0.6
Tj=
C 25
96 94
200KHz
0.4
Tj=0C
92 90
0.2
88 86
IO = 3A VCC = 50V
0
0
1
2
3
IO(A)
0
10
20
30
40 VO(V)
Figure 18: Efficiency vs. Output Voltage (Diode STPS745D)
(%) 98
100KHz
Figure 19: Efficiency vs. Output Current ( see fig.1c)
(%)
D97IN645
D97IN642
96 94 92 90 88 86 0 5 10 15 20 25 30 VO (V)
IO = 3A VCC = 35V 200KHz
95
Vcc=12V
VO = 5.1V fsw = 100KHz
90
Vcc=24V
85
Vcc=48V
80
0
1
2
3
IO(A)
Figure 20: Efficiency vs. Output Current (see fig.1c)
(%)
Vcc=12V
Figure 21: Efficiency vs. Output Current (see fig.1d)
(%)
D97IN644
D97IN646
90
Vcc=24V
90
Vcc=12V
V O = 3.3V fsw = 100KHz
85
Vcc=48V
85
Vcc=24V
80
VO = 5.1V fsw = 200KHz
80
Vcc=48V
75
10/16
0
1
2
3
IO (A)
75
0
1
2
3
IO(A)
L4973V3 - L4973V5 - L4973D3 - L4973D5
Figure 22: Efficiency vs. Output Current (see fig.1d)
(%) 90
Vcc=12V
Figure 23: Power dissipation vs. Input Voltage (Device only) (see fig.1c)
Pdiss (W)
D97IN647A
VO = 5.1V fsw = 100KHz
D97IN662
VO = 3.3V fsw = 200KHz
1.5
IO =3.5A
85
Vcc=24V
1.0
IO =3A
80
Vcc=48V
IO=2.5A
75 70
0.5
IO =2A
0
0.5
1
1.5
2
2.5
3
3.5 IO (A)
0
0
10
20
30
40
50
Vcc(V)
Figure 24: Power dissipation vs. Output Voltage (Device only)
Pdiss (W) 3.0 2.5
VCC = 35V fsw = 100KHz
Figure 25: Pulse by Pulse Limiting Current vs. Junction Temperature
Ilim (A) 5.2 5
D97IN652
D97IN648
I O =3.5A
2.0 1.5 1.0 0.5 0
I O=3A
4.8
IO =2.5A
Vcc=35
IO =2A I O =1A
4.6 4.4 4.2 -40 -20 0
0
5
10
15
20
25
30
V O(V)
20 40 60 80 100 120
Tj(C)
Figure 26: Load Transient
IO (A) 3 2 1 2
200s/DIV
T
Figure 27: Line Transient
D97IN649
VCC (V) 30 20 10 VO (mV) 100 1
D97IN650
VO (mV)
I O = 1A f sw = 100KHz
100 0 -100
1
T
0
VCC = 35V fsw = 100KHz
2
-100
1ms/DIV
11/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
Figure 28: Source Current Rise and Fall Time, pin 2, 3 (See fig1) Figure 29: Soft Start Capacitor Selection vs. Inductor and VCC max (ref. AN938)
Lomax (H) 300 250
Css=680nF fsw = 100KHz
D97IN653
Css=1F Css=820nF
200 150 100 50 0
Css=470nF
Css=220nF Css=100nF
25
30
35
40
45
50
Vi(V)
Figure 30:Soft Start Capacitor Selection vs. Inductor and VCC max (ref. AN938)
Lomax (H)
nF 68 Cs
Figure 31: Open Loop Frequency and Phase of Error amplifier
GAIN (dB) 50
GAIN
D97IN654
nF
D97IN663
Phase
150
nF Cs s=
Cs
f sw = 200KHz
s=
s=
56
0 -50 -100
Phase
100
Cs s 3 =3 nF
47
0 45 90 135
50
Cs
s
2 =2
nF
-150 -200
0 15 20 25 30 35 40 45 50 Vi(V)
10
102 103 104 105 106 107 108 f(Hz)
Figure 32: 3.5A at VO< 3.3V (see part list fig. 1)
VP 1 VCC R2 INH SYNC 1.5 2 2.5 7,8 1 17 C1 C2 C7 11 16 10 18 9 C8 L1 2,3 12 3 R5 3.6K 2K 4.7K 7.5K 5.1K R3 4.7K 2K 3.6K 3.6K 1K Vo VO=3.36-1.74* R3 R5
L4973V3.3
4,5,6 13,14,15
R5 C3 C5 R1 C6 C4
D1
3x C0
R3
D97IN666A
12/16
L4973V3 - L4973V5 - L4973D3 - L4973D5
Figure 33: 12V to 3.3V High Performance Buck Converter (fsw = 200kHz)
INH VCC 12V5% R2 22k C7 1.2nF C1 560uF-25V HFQ Panasonic C2 220nF
SYNC C8 220nF L1 2,3 12 Vo=3.33V Io=3.5A D1 C9 470uF-25V HFQ Panasonic (%) 92 90 88 86 84 82
7,8 1 17 16
10
18
9
L4973V3.3
11 4,5,6 13,14,15
C3 33nF
C4 1uF
C5 220pF
R1 9k1 C6 22nF
L1 D1
KoolMm 77120- 24 Turns- 0.9mm STPS1025
D97IN668A
80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Io(A)
Figure 34: Synchronization Example
VCC2 V CC1 VCC
7,8 1
7,8 18 18
7,8 1 1
18
18
7,8
L4973
4,5,6 13,14,15
L4973
4,5,6 13,14,15
L4973
4,5,6 13,14,15 1
L4973
4,5,6 13,14,15
D97IN669
Figure 35: Multioutput not Isolated (Pin out referred to DIP12+3+3)
V CC R2
INH
SYNC C8 D2 Vo2
7,8 1 17
10
18
9 n2 2,3 L1 n1 Vo1
L4973
11 4,5,6 13,14,15 12
C1
C2
C7
16
C3
C4
C5
R1 C6
D1
C9
C10
C11
V O2 = VO1
n1 + n 2 n1
D97IN667A
PO2 < 20% P O1
13/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.30 2.54 8.80 2.54 20.32 7.10 5.10 0.130 0.100 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.800 0.280 0.201 0.015 1.40 mm TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.976 0.055 inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
Powerdip 18
14/16
L4973V3 - L4973V5 - L4973D3 - L4973D5
mm MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299
DIM.
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
15/16
L4973V3.3 - L4973V5.1 - L4973D3.3 - L4973D5.1
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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